The exemplary embodiments of this invention relate generally to semiconductor devices and, more specifically, to semiconductor devices having raised sources/drains and replacement metal gates formed by selective metal deposition.
A semiconductor device such as a field effect transistor (FET) can be fabricated on a bulk semiconductor substrate or on a silicon-on-insulator (SOI) substrate. The FET (or other device) may have source and drain regions that protrude above the surface of the substrate to define raised sources and drains. A gate overlies a channel extending between the raised sources and drains and controls the flow of current between the source and drain regions.
In forming a gate for a semiconductor device having raised sources and drains, a dummy gate is formed on the substrate, and the raised sources and drains are formed around the dummy gate. The dummy gate is then removed and replaced by an electrically conductive metal-containing gate (a replacement metal gate (RMG)). An interlayer dielectric (ILD) may be used to cover the raised sources and drains while removing the dummy gate structure. The ILD is then subjected to a chemical-mechanical polish (CMP).
During the CMP of the ILD, the raised sources and drains may be exposed. Once the raised sources and drains are exposed, materials used to remove the dummy gate (e.g., acid etchants) may undesirably affect the material of the raised sources and drains.